1. Field of the Invention
The present invention relates to a field effect transistor (FET) and a process for fabricating the same. More particularly the present invention is directed to a compound semiconductor FET with a high transconductance and a process for fabricating the same.
2. Description of the Prior Art
Gallium arsenide (GaAs) integrated circuits (IC's) are promising as high speed devices for telecommunications and computers as an alternative to silicon (Si) large scale integrated circuits (LSI's) and are, therefore, under vigorous investigation. For example, recently GaAs LSI's; such as a 16.times.16-bit multiplier and a 1k-bit static random access memory have been successfully fabricated. In order to improve the output-current-drive; capability and the degree of integration of the GaAs LSI's, it is necessary to decrease the size of an element of a GaAs LSI, and to increase the transconductance g.sub.m of a GaAS FET.
The g.sub.m of an FET is expressed by the following formula: ##EQU1## wherein .epsilon. is the dielectric constant of the GaAS, .mu. the carrier mobility, W.sub.g the gate width, d the effective channel layer thickness, L.sub.g the gate length, V.sub.gs the voltage applied between the gate and source electrodes, and V.sub.th the threshold voltage. The g.sub.m per unit gate width having fixed V.sub.th can be increased by shortening L.sub.g, increasing .mu., or reducing d, in accordance with constant .epsilon.. The common way to decrease the device size and the gate capacitance is to shorten the gate length. Although most conventional semiconductors are of silicon, compound semiconductors such as GaAs are now under investigation, snce they have a larger .mu. than that of silicon. The present invention is directed to reducing of d, i.e., to reducing the effective channel layer thickness.
Recently, the channel layer of an FET of a compound semiconductor LSI, such as a GaAS LSI, is, in general, formed by an ion implantation technique. The depth distribution of the concentration of implanted ions in the channel layer becomes approximately the Gaussian distribution given in the Lindhard, Scharf, and Schiott theory, and the effective channel layer thickness d can be considered to be approximately ##EQU2## wherein R.sub.p is the mean projected range and .sigma. the standard deviation of the projected range. When the kinds of the material of the compound semiconductor substrate to be ion-implanted and the ions which should be implanted into the substrate are given, the decrease in the ion implanting energy causes a decrease in both R.sub.p and .sigma., reducing the effective channel layer thickness d. The decrease in the ion implanting energy is, however, limited by the capability of the ion implantation apparatus along with increasing the sputtering effects; and causes problems such as a decrease in the controllability and in the uniformity of the ion implantation and a decrease in the carrier mobility.
Further, conventional ion implantation techniques and the subsequent heat treatment for activating the ions produce problems such as dispersion of the threshold voltage. Ion implantation into a bare compound semiconductor substrate may enhance dissociation of the components and oxidation at the surface of the substrate. Ion implantation through an insulating layer into a compound semiconductor substrate causes the incorporation of the element atoms of the insulating layer into the compound semiconductor substrate, which may have an adverse effect on the compound semiconductor. Heat treatment after ion implantation to activate the implanted ions may cause strains in the substrate due to the difference in the heat expansion coefficients of the substrate and surface protective layers. These result in defects and nonuniform carrier distribution of a channel layer formed in the compound semiconductor substrate, causing nonuniform distribution of the threshold voltages of the FET's across a wafer. Decreasing the standard deviation of the threshold voltage is necessary in order to increase the degree of integration of the LSI's.
One of the inventors of the present invention has already proposed the use of an aluminum nitride (AlN) layer as a protective film for both the ion-implantation and the subsequent heat treatment. In the proposed method, the ions are implanted through the aluminum nitride layer. However, the trend is to use a thinner aluminum nitride layer as a protective film for the ion implantation and, therefore, the threshold voltages may vary at different portions of the wafer. The deviation of the threshold voltages of FET's, AV.sub.th, is an important problem in fabricating GaAS LSI's. At present, when 1k-bit LSI's are fabricated, .DELTA.V.sub.th is allowed up to approximately 60 mV, which can be attained by the prior art though the yield of the LSI's is low. However, when 4k to 64k-bit LSI's are to be fabricated, .DELTA.V.sub.th should be decreased, for example, in the range of approximately 50 to 20 mV, which cannot be attained by the prior art as mentioned above.